PIC16CR83 Datasheet

IC型号：
PIC16CR83
PDF描述：
18-pin Flash/EEPROM 8-Bit Microcontrollers
文件大小：
2018.18KB
PDF页数：
125页
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PIC16F8X

8.9

Interrupts

The PIC16F8X has 4 sources of interrupt:

鈥?/div>

External interrupt RB0/INT pin

TMR0 over铿俹w interrupt

PORTB change interrupts (pins RB7:RB4)

Data EEPROM write complete interrupt

The RB0/INT pin interrupt, the RB port change inter-

rupt and the TMR0 over铿俹w interrupt 铿俛gs are con-

tained in the INTCON register.

When an interrupt is responded to; the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. For external interrupt events, such as the

RB0/INT pin or PORTB change interrupt, the interrupt

latency will be three to four instruction cycles. The exact

latency depends when the interrupt event occurs

(Figure 8-17). The latency is the same for both one and

two cycle instructions. Once in the interrupt service

routine the source(s) of the interrupt can be determined

by polling the interrupt 铿俛g bits. The interrupt 铿俛g bit(s)

must be cleared in software before re-enabling

interrupts to avoid in铿乶ite interrupt requests.

The interrupt control register (INTCON) records

individual interrupt requests in 铿俛g bits. It also contains

the individual and global interrupt enable bits.

The global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. Bit GIE is cleared on reset.

The 鈥渞eturn from interrupt鈥?instruction,

RETFIE,

exits

interrupt routine as well as sets the GIE bit, which

re-enable interrupts.

Note 1:

Individual interrupt 铿俛g bits are set

regardless of the status of their

corresponding mask bit or the GIE bit.

FIGURE 8-16: INTERRUPT LOGIC

T0IF

T0IE

INTF

INTE

RBIF

RBIE

EEIF

EEIE

GIE

Wake-up

(If in SLEEP mode)

Interrupt to CPU

漏

1998 Microchip Technology Inc.

DS30430C-page 47

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