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SC16C754BIBM-S Datasheet

  • SC16C754BIBM-S

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  • Philips

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Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Remark:
Refer to the notes under
Table 9
for more register access information.
7.1 Receiver holding register (RHR)
The receiver section consists of the receiver holding register (RHR) and the receiver
shift register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial
data from the RX terminal. The data is converted to parallel data and moved to the
RHR. The receiver section is controlled by the line control register. If the FIFO is
disabled, location zero of the FIFO is used to store the characters.
Remark:
In this case, characters are overwritten if over铿俹w occurs.
If over铿俹w occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
7.2 Transmit holding register (THR)
The transmitter section consists of the transmit holding register (THR) and the
transmit shift register (TSR). The THR is actually a 64-byte FIFO. The THR receives
data and shifts it into the TSR, where it is converted to serial data and moved out on
the TX terminal. If the FIFO is disabled, the FIFO is still used to store the byte.
Characters are lost if over铿俹w occurs.
9397 750 11618
漏 Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 鈥?19 June 2003
22 of 49

SC16C754BIBM-S 产品属性

  • NXP

  • UART 接口集成电路

  • 4

  • 5 Mbps

  • 5.5 V

  • 2.25 V

  • 6 mA

  • + 85 C

  • - 40 C

  • LQFP-64

  • Bulk

  • SMD/SMT

  • 2.5 V, 3.3 V, 5 V

  • 250

  • SC16C754BIBM,151

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