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SC16C754BIBM-S Datasheet

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Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
7.5 Line status register (LSR)
Table 13
shows the line status register bit settings.
Table 13:
Bit
7
Line Status Register bits description
Description
FIFO data error.
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error, or break indication is
in the receiver FIFO. This bit is cleared when no more errors are
present in the FIFO.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator.
Logic 0 = Transmitter hold
and
shift registers are not empty.
Logic 1 = Transmitter hold
and
shift registers are empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator.
Logic 0 = Transmit hold register is
not
empty.
Logic 1 = Transmit hold register is empty. The processor can now load
up to 64 bytes of data into the THR if the TX FIFO is enabled.
4
LSR[4]
Break interrupt.
Logic 0 = No break condition (normal default condition).
Logic 1 = A break condition occurred and associated byte is 00, i.e.,
RX was LOW for one character time frame.
3
LSR[3]
Framing error.
Logic 0 = No framing error in data being read from RX FIFO (normal
default condition).
Logic 1 = Framing error occurred in data being read from RX FIFO, i.e.,
received data did not have a valid stop bit.
2
LSR[2]
Parity error.
Logic 0 = No parity error (normal default condition).
Logic 1 = Parity error in data being read from RX FIFO.
1
LSR[1]
Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error has occurred.
0
LSR[0]
Data in receiver.
Logic 0 = No data in receive FIFO (normal default condition).
Logic 1 = At least one character in the RX FIFO.
Symbol
LSR[7]
When the LSR is read, LSR[4:2] re铿俥ct the error bits (BI, FE, PE) of the character at
the top of the RX FIFO (next character to be read). The LSR[4:2] registers do not
physically exist, as the data read from the RX FIFO is output directly onto the output
data bus, DI[4:2], when the LSR is read. Therefore, errors in a character are identi铿乪d
by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only
when there are no more errors remaining in the FIFO.
Reading the LSR does not cause an increment of the RX FIFO read pointer. The
RX FIFO read pointer is incremented by reading the RHR.
9397 750 11618
漏 Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 鈥?19 June 2003
25 of 49

SC16C754BIBM-S 产品属性

  • NXP

  • UART 接口集成电路

  • 4

  • 5 Mbps

  • 5.5 V

  • 2.25 V

  • 6 mA

  • + 85 C

  • - 40 C

  • LQFP-64

  • Bulk

  • SMD/SMT

  • 2.5 V, 3.3 V, 5 V

  • 250

  • SC16C754BIBM,151

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