DS26502 T1/E1/J1/64KCC BITS Element
3. BLOCK DIAGRAMS
Figure 3-1. Block Diagram
MCLK
DS26502
MASTER CLOCK
RTIP
RRING
RLOS
CLOCK
+ DATA
- DATA
JA CLOCK
RCLK
LOF_CCE
RX
RX
LIU
LIU
L
O
C
A
L
L
O
O
P
B
A
C
K
JA
ENABLED
AND IN RX
PATH
R
E
M
O
T
E
L
O
O
P
B
A
C
K
M
U
X
T1/E1 SSM
FRAMER
64KCC
DECODER
TX PLL
CLOCK
MUX
RSER
RS_8K
400HZ
RAIS
TNEGO
TPOSO
JITTER
ATTENUATOR
CAN BE
ASSIGNED TO
RECEIVE OR
TRANSMIT PATH
OR DISABLED
TCLK
PLL_OUT
TTIP
TRING
TX
LIU
M
U
X
TX CLOCK
+ DATA
- DATA
JA
ENABLED
AND IN TX
PATH
T1/E1 SSM
FORMATTER
64KCC
CODER
TSER
TS_8K_4
THZE
TCLKO
JTAG PORT
JTAG
PORT
JTMS JTRST JTCLK JTDI
JTDO
PARALLEL/SERIAL CPU I/F
HARDWARE CONTROLLER
BIS1
PARALLEL,
SERIAL, OR
HARDWARE
CONTROLLER
BIS0
TSTRST
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