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DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

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DS26502 T1/E1/J1/64KCC BITS Element
7.4 Interrupt Handling
Various alarms, conditions, and events in the DS26502 can cause interrupts. For simplicity, these are all
referred to as events in this explanation. All STATUS registers can be programmed to produce interrupts.
Each status register has an associated interrupt mask register. For example, SR1 (Status Register 1) has an
interrupt control register called IMR1 (Interrupt Mask Register 1). Status registers are the only sources of
interrupts in the DS26502. On power-up, all writeable registers are automatically cleared. Since bits in
the IMRx registers have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can
occur until the host selects which events are to product interrupts. Since there are potentially many
sources of interrupts on the DS26502, several features are available to help sort out and identify which
event is causing an interrupt. When an interrupt occurs, the host should first read the IIR register
(interrupt information register) to identify which status register(s) is producing the interrupt. Once that is
determined, the individual status register or registers can be examined to determine the exact source.
Once an interrupt has occurred, the interrupt handler routine should clear the IMRx registers to stop
further activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt
hander routine should restore the state of the IMRx registers.
7.5 Status Registers
When a particular event or condition has occurred (or is still occurring in the case of conditions), the
appropriate bit in a status register will be set to a one. All the status registers operate in a latched fashion,
which means that if an event or condition occurs a bit is set to a one. It will remain set until the user reads
that bit. An event bit will be cleared when it is read and it will not be set again until the event has
occurred again. Condition bits such as RLOS, etc., will remain set if the alarm is still present.
The user will always precede a read of any of the status registers with a write. The byte written to the
register will inform the DS26502 which bits the user wishes to read and have cleared. The user will write
a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the
bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit
location, the read register will be updated with the latest information. When a zero is written to a bit
position, the read register will not be updated and the previous value will be held. A write to the status
registers will be immediately followed by a read of the same register. This write-read scheme allows an
external microcontroller or microprocessor to individually poll certain bits without disturbing the other
bits in the register. This operation is key in controlling the DS26502 with higher-order languages.
Status register bits are divided into two groups: condition bits and event bits. Condition bits are typically
network conditions such as loss of frame, or all-ones detect. Event bits are typically markers such as the
one-second timer. Each status register bit is labeled as a condition or event bit. Some of the status
registers have bits for both the detection of a condition and the clearance of the condition. For example,
SR2 has a bit that is set when the device goes into a loss of frame state (SR2.0, a condition bit) and a bit
that is set (SR2.4, an event bit) when the loss of frame condition clears (goes in sync). Some of the status
register bits (condition bits) do not have a separate bit for the 鈥渃ondition clear鈥?event but rather the status
bit can produce interrupts on both edges, setting, and clearing. These bits are marked as 鈥渄ouble interrupt
bits.鈥?An interrupt will be produced when the condition occurs and when it clears.
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