DS26502 T1/E1/J1/64KCC BITS Element
Figure 3-4. Master Clock PLL Diagram
MCLK PIN
PRE-SCALER
DIVIDE BY 1, 2, 4,
OR 8
X12,X16
MULTIPLIER
PLL
LIC4.6
(MPS0)
LIC4.7
(MPS1)
JA CLOCK
2.048MHz to
1.544MHz PLL
TO CLOCK AND DATA
RECOVERY ENGINE IN
RECEIVE LIU
LIC2.3
(JACKS)
(HARDWARE MODE PIN NAME)
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