DS26502 T1/E1/J1/64KCC BITS Element
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
7
RAIS-CI
0
X
SR3
Status Register 3
18h
6
LOTC
0
X
5
BOCC
0
X
4
RFDLAD
0
X
3
RFDLF
0
X
2
TFDLE
0
X
1
RMTCH
0
X
0
RBOC
0
X
Bit 0: Receive BOC Detector Change-of-State Event (RBOC).
Set whenever the BOC detector sees a change of state to a
valid BOC. The setting of this bit prompts the user to read the RFDL register.
Bit 1: Receive FDL Match Event (RMTCH).
Set whenever the contents of the RFDL register matches RFDLM1 or
RFDLM2.
Bit 2: TFDL Register Empty Event (TFDLE).
Set when the transmit FDL buffer (TFDL) empties.
Bit 3: RFDL Register Full Event (RFDLF).
Set when the receive FDL buffer (RFDL) fills to capacity.
Bit 4: RFDL Abort Detect Event (RFDLAD).
Set when eight consecutive ones are received on the FDL.
Bit 5: BOC Clear Event (BOCC).
Set when 30 FDL bits occur without an abort sequence.
Bit 6: Loss Of Transmit Clock Event (LOTC).
Set when the signal at the TCLK pin has not transitioned for approximately
15 periods of the scaled MCLK.
Bit 7: Receive AIS-CI Event (RAIS-CI).
(T1 Only) Set when the receiver detects the AIS-CI pattern as defined in ANSI
T1.403.
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