鈥?/div>
Bits 0 to 2: Receive Termination Select (RT0 to RT1)
RT2
0
0
0
0
1
RT1
0
0
1
1
0
RT0
0
1
0
1
0
INTERNAL RECEIVE
TERMINATION CONFIGURATION
Internal Receive-Side Termination Disabled
Internal Receive-Side 75鈩?Enabled
Internal Receive-Side 100鈩?Enabled
Internal Receive-Side 120鈩?Enabled
Internal Receive-Side 110鈩?Enabled
Internal Receive-Side Termination Disabled
Internal Receive-Side Termination Disabled
Internal Receive-Side Termination Disabled
1
1
1
0
1
1
1
0
1
Bits 3 to 5:Transmit Termination Select (TT0 to TT1)
TT2
0
0
0
0
1
1
1
1
TT1
0
0
1
1
0
0
1
1
TT0
0
1
0
1
0
1
0
1
INTERNAL TRANSMIT
TERMINATION CONFIGURATION
Internal Transmit-Side Termination Disabled
Internal Transmit-Side 75鈩?Enabled
Internal Transmit-Side 100鈩?Enabled
Internal Transmit-Side 120鈩?Enabled
Internal Transmit-Side 110鈩?Enabled
Internal Transmit-Side Termination Disabled
Internal Transmit-Side Termination Disabled
Internal Transmit-Side Termination Disabled
Bits 6 and 7: MCLK Prescaler (MPS0 to MPS1) (T1 Mode)
MCLK (MHz)
1.544
3.088
6.176
12.352
2.048
4.096
8.192
16.384
MPS1
0
0
1
1
0
0
1
1
MPS0
0
1
0
1
0
1
0
1
JACKS (LIC2.3)
0
0
0
0
1
1
1
1
Bits 6 and 7: MCLK Prescaler (MPS0 to MPS1) (E1 Mode)
MCLK (MHz)
2.048
4.096
8.192
16.384
MPS1
0
0
1
1
MPS0
0
1
0
1
JACKS (LIC2.3)
0
0
0
0
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