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DS26502数据手册封面

DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

  • 1043.62KB

  • 125页

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DS26502 T1/E1/J1/64KCC BITS Element
9. E1 FRAMER/FORMATTER CONTROL REGISTERS
The E1 framer portion of the DS26502 is configured via a set of two control registers. Typically, the
control registers are only accessed when the system is first powered up. Once the DS26502 has been
initialized, the control registers will only need to be accessed when there is a change in the system
configuration. There is one receive control register (E1RCR) and one transmit control register (E1TCR).
There are also two information registers and a status register, as well as an interrupt mask register. Each
of these registers is described in this section.
9.1 E1 Control Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
7
鈥?/div>
0
0
E1RCR
E1 Receive Control Register
1Dh
6
RLOSA
0
0
5
RHDB3
0
HBE
PIN 55
4
鈥?/div>
0
0
3
鈥?/div>
0
0
2
FRC
0
0
1
SYNCE
0
0
0
RESYNC
0
0
Bit 0: Resync (RESYNC).
When toggled from low to high, a resync is initiated. Must be cleared and set again for a
subsequent resync.
Bit 1: Sync Enable (SYNCE)
0 = auto resync enabled
1 = auto resync disabled
Bit 2: Frame Resync Criteria (FRC)
0 = resync if FAS received in error three consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times
Bits 3, 4, 7: Unused, must be set = 0 for proper operation.
Bit 5: Receive HDB3 Enable (RHDB3)
0 = HDB3 disabled
1 = HDB3 enabled
Bit 6: Receive Loss Of Signal (RLOS). Alternate Criteria (RLOSA).
Defines the criteria for a Receive Loss Of Signal
condition.
0 = RLOS declared upon 255 consecutive zeros (125碌s)
1 = RLOS declared upon 2048 consecutive zeros (1ms)
45 of 124

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