DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

  • 1043.62KB

  • 125页

  • MAXIM

扫码查看芯片数据手册

上传产品规格书

PDF预览

DS26502 T1/E1/J1/64KCC BITS Element
Table 9-1. E1 Sync/Resync Criteria
FRAME OR
MULTIFRAME
LEVEL
FAS
SYNC CRITERIA
FAS present in frame N and
N + 2, and FAS not present in
frame N + 1
RESYNC CRITERIA
Three consecutive incorrect FAS
received
Alternate: (E1RCR.2 = 1) The above
criteria is met or three consecutive
incorrect bit 2 of non-FAS received
915 or more CRC4 code words out of
1000 received in error
Two consecutive MF alignment
words received in error
ITU SPEC.
G.706
4.1.1
4.1.2
CRC4
CAS
Two valid MF alignment
words found within 8ms
Valid MF alignment word
found and previous time slot
16 contains code other than
all zeros
G.706
4.2 and 4.3.2
G.732 5.2
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
7
TFPT
0
0
E1TCR
E1 Transmit Control Register
1Eh
6
鈥?/div>
0
0
5
鈥?/div>
0
0
4
TSiS
0
0
3
鈥?/div>
0
0
2
鈥?/div>
0
0
1
THDB3
0
HBE
PIN 55
0
鈥?/div>
0
0
Bits 0, 2, 3, 5, 6:Unused, must be set = 0 for proper operation.
Bit 1: Transmit HDB3 Enable (THDB3)
0 = HDB3 disabled
1 = HDB3 enabled
Bit 4: Transmit International Bit Select (TSiS)
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode, E1TCR1.7 must be set to 0)
Bit 7: Transmit Time Slot 0 Pass-Through (TFPT)
0 = FAS bits/Sa bits/remote alarm sourced internally from the TAF and TNAF registers
1 = FAS bits/Sa bits/remote alarm sourced from TSER
46 of 124

DS26502 PDF文件相关型号

DS26502LN

DS26502相关型号PDF文件下载

扫码下载APP,
一键连接广大的电子世界。

在线人工客服

买家服务:
卖家服务:

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号,
第一时间获取资讯。

建议反馈

联系人:

联系方式:

按住滑块,拖拽到最右边
>>
感谢您向阿库提出的宝贵意见,您的参与是维库提升服务的动力!意见一经采纳,将有感恩红包奉上哦!