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DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

  • 1043.62KB

  • 125页

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DS26502 T1/E1/J1/64KCC BITS Element
13.1 LIU Operation
The LIU interfaces the T1, E1, 64KCC, and 6312kHz signals to the various types of network media
through coupling transformers. The LIU transmit and receive functions are independent. For example, the
receiver can be in T1 mode while the transmitter is in E1 mode. The 6312kHz transmission is an
exception to the other modes. For transmission, 6312kHz is only available as a 0 to 3.3V signal on the
TCLKO pin. It is not output to the TTIP and TRING pins for coupling to twisted pair. Because the G.703
specifications of the transmit pulse shape for Japanese 6312kHz are unclear, the user can externally filter
this signal to generate a sine wave type of signal. However, on the receive side, 6312kHz can be input
through the receive transformer to the RTIP and RRING pins.
13.2 LIU Receiver
The analog AMI/HDB3 E1 waveform, AMI/B8ZS T1 waveform, or AMI 64KCC waveform is
transformer-coupled into the RTIP and RRING pins of the DS26502. The user has the option to use
internal termination, software-selectable for 75/100/110/120W applications, or external termination. The
LIU recovers clock and data from the analog signal and passes it through the jitter attenuation mux.
(Note: The jitter attenuator is only available in T1 or E1 mode.) The DS26502 contains an active filter
that reconstructs the analog-received signal for the nonlinear losses that occur in long-haul T1 and E1
transmission. The receiver is configurable for various T1 and E1 monitor applications. The device has a
usable receive sensitivity of 0dB to 鈥?3dB for E1 and 0dB to 鈥?6dB for T1, which allows the device to
operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6000ft (T1) in length.
The DS26502鈥檚 LIU is designed to be fully software selectable for E1 and T1 without the need to change
any external resistors for the receive-side. The receiver will allow the user to configure the DS26502 for
75鈩? 100鈩? 110鈩? or 120鈩?receive termination by setting the RT0(LIC4.0), RT1(LIC4.1), and
RT2(LIC4.2). When using the internal termination feature, the resistors labeled R in
Figure 13-4
should
be 60鈩?each. If external termination is used, RT0, RT1, and RT2 should be set to zero and the resistors
labeled R in
Figure 13-4
will need to be 37.5鈩? 50鈩? 55鈩? or 60鈩?each, depending on the required
termination.
There are two ranges of receive sensitivity for T1 and E1, which is selectable by the user. The EGL bit of
LIC1 (LIC1.4) selects the full or limited sensitivity.
Normally, the clock that is output at the RCLK pin is the recovered clock from the waveform presented at
the RTIP and RRING inputs. If the jitter attenuator is placed in the receive path (as is the case in most
applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If the jitter
attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter
high cycles of the clock. This is due to the highly over-sampled digital clock recovery circuitry. See the
Receive AC Timing Characteristics
section for more details. When no signal is present at RTIP and
RRING, a receive loss of signal (RLOS) condition will occur and the signal at RCLK will be derived
from the scaled signal present on the MCLK pin JACLK.
13.2.1 Receive Level Indicator
The DS26502 will report the signal strength at RTIP and RRING in 2.5dB increments via RL3-RL0
located in the Information Register 1 (INFO1). This feature is helpful when trouble shooting line
performance problems.
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