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DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

  • 1043.62KB

  • 125页

  • MAXIM

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DS26502 T1/E1/J1/64KCC BITS Element
7.7
8.
8.1
9.
9.1
9.2
10.
11.
11.1
11.2
11.3
12.
12.1
12.2
13.
I
NTERRUPT
I
NFORMATION
R
EGISTERS
..............................................................................38
T1 FRAMER/FORMATTER CONTROL REGISTERS ....................................................39
T1 C
ONTROL
R
EGISTERS
...............................................................................................39
E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................45
E1 C
ONTROL
R
EGISTERS
...............................................................................................45
E1 I
NFORMATION
R
EGISTERS
..........................................................................................47
I/O PIN CONFIGURATION OPTIONS ............................................................................51
T1 SYNCHRONIZATION STATUS MESSAGE ..............................................................54
T1 B
IT
-O
RIENTED
C
ODE
(BOC) C
ONTROLLER
................................................................54
T
RANSMIT
BOC.............................................................................................................54
R
ECEIVE
BOC...............................................................................................................55
E1 SYNCHRONIZATION STATUS MESSAGE ..............................................................63
S
A
/S
I
B
IT
A
CCESS
B
ASED ON
CRC4 M
ULTIFRAME
...........................................................63
A
LTERNATE
S
A
/S
I
B
IT
A
CCESS
B
ASED ON
D
OUBLE
-F
RAME
...............................................73
LINE INTERFACE UNIT (LIU) ........................................................................................76
13.1 LIU O
PERATION
............................................................................................................77
13.2 LIU R
ECEIVER
..............................................................................................................77
13.2.1 Receive Level Indicator ............................................................................................77
13.2.2 Receive G.703 Section 10 Synchronization Signal ..................................................78
13.2.3 Monitor Mode ...........................................................................................................78
13.3 LIU T
RANSMITTER
.........................................................................................................78
13.3.1 Transmit Short-Circuit Detector/Limiter ....................................................................79
13.3.2 Transmit Open-Circuit Detector................................................................................79
13.3.3 Transmit BPV Error Insertion ...................................................................................79
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)................................79
13.4 MCLK P
RE
-S
CALER
......................................................................................................79
13.5 J
ITTER
A
TTENUATOR
......................................................................................................79
13.6 CMI (C
ODE
M
ARK
I
NVERSION
) O
PTION
...........................................................................80
13.7 LIU C
ONTROL
R
EGISTERS
.............................................................................................81
13.8 R
ECOMMENDED
C
IRCUITS
..............................................................................................89
14.
15.
15.1
15.2
16.
16.1
16.2
17.
17.1
17.2
LOOPBACK CONFIGURATION.....................................................................................94
64KHZ SYNCHRONIZATION INTERFACE....................................................................95
R
ECEIVE
64
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
............................................95
T
RANSMIT
64
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
..........................................96
6312KHZ SYNCHRONIZATION INTERFACE................................................................97
R
ECEIVE
6312
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
........................................97
T
RANSMIT
6312
K
H
Z
S
YNCHRONIZATION
I
NTERFACE
O
PERATION
.......................................97
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................98
I
NSTRUCTION
R
EGISTER
...............................................................................................102
T
EST
R
EGISTERS
.........................................................................................................103
3 of 124

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