DS26502 T1/E1/J1/64KCC BITS Element
17. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS26502 supports the standard IEEE 1149.1 instruction codes SAMPLE/PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26502
contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture:
搂
搂
搂
搂
搂
搂
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990,
IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins:
JTRST,
JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Figure 17-1. JTAG Functional Block Diagram
BOUNDRY SCAN
REGISTER
IDENTIFICATION
REGISTER
BYPASS
REGISTER
INSTRUCTION
REGISTER
TEST ACCESS PORT
CONTROLLER
V
DD
10kW
10kW
MUX
SELECT
OUTPUT ENABLE
V
DD
V
DD
10kW
JTDI
JTMS
JTCLK
JTRST
JTDO
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