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DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

  • 1043.62KB

  • 125页

  • MAXIM

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DS26502 T1/E1/J1/64KCC BITS Element
9.2 E1 Information Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
7
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0
X
INFO2
Information Register 2
12h
6
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0
X
5
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0
X
4
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0
X
3
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0
X
2
CRCRC
0
X
1
FASRC
0
X
0
CASRC
0
X
Bit 0: CAS Resync Criteria Met Event (CASRC).
Set when two consecutive CAS MF alignment words are received in
error.
Bit 1: FAS Resync Criteria Met Event (FASRC.
Set when three consecutive FAS words are received in error.
Bit 2: CRC Resync Criteria Met Event (CRCRC).
Set when 915/1000 codewords are received in error.
Bits 3 to 7: Unused
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
7
CSC5
0
X
INFO3
Information Register 3 (Real Time)
1Ch
6
CSC4
0
X
5
CSC3
0
X
4
CSC2
0
X
3
CSC0
0
X
2
FASSA
0
X
1
CASSA
0
X
0
CRC4SA
0
X
Bit 0: CRC4 MF Sync Active (CRC4SA).
Set while the synchronizer is searching for the CRC4 MF alignment word.
Bit 1: CAS MF Sync Active (CASSA).
Set while the synchronizer is searching for the CAS MF alignment word.
Bit 2: FAS Sync Active (FASSA).
Set while the synchronizer is searching for alignment at the FAS level.
Bits 3 to 7: CRC4 Sync Counter Bits (CSC0 and CSC2 to CSC4).
The CRC4 sync counter increments each time the 8ms-
CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the
CRC4 level. The counter can also be cleared by disabling the CRC4 mode (E1RCR.3 = 0). This counter is useful for
determining the amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that
if synchronization at the CRC4 level cannot be obtained within 400ms, then the search should be abandoned and proper action
taken. The CRC4 sync counter will rollover. CSC0 is the LSB of the 6-bit counter. (Note: The second LSB, CSC1, is not
accessible. CSC1 is omitted to allow resolution to >400ms using 5 bits.)
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