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DS26502数据手册封面

DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

  • 1043.62KB

  • 125页

  • MAXIM

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DS26502 T1/E1/J1/64KCC BITS Element
Bits 4 to 7: Transmit Mode Configuration (TMODE[3:0]).
Used to select the operating mode of the transmit path for the
DS26502.
TMODE3
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Note 1:
TMODE2
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
TMODE1
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
TMODE0
0
1
0
1
0
0
1
0
0
1
0
1
0
1
0
1
Transmit Path Operating Mode
T1 D4
T1 ESF
(Note: In this mode the TFSE (T1TCR2.6) bit should be
set = 0.)
J1 D4
J1 ESF
E1 FAS
E1 FAS + CAS
(Note 1)
Reserved
E1 CRC4
E1 CRC4 + CAS
(Note 1)
Reserved
E1 G.703 2048 kHz Synchronization Interface
64kHz + 8kHz Synchronization Interface
64kHz + 8kHz + 400Hz Synchronization Interface
6312kHz Synchronization Interface
(Note 2)
Reserved
Reserved
Note 2:
The DS26502 does not have an internal source for CAS signaling and multiframe alignment generation. CAS signaling, and the
multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present on the TSER pin and frame
aligned to sync signal on the TS_8K_4 pin.
In addition to setting the TMODE bits to 6312kHz Synchronization Interface mode, the Transmit PLL must also be configured to
transmit a 6312kHz signal through the Transmit PLL Control Register (TPCR.6 and TPCR.7)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
7
TPLLOFS1
0
0
TPCR
Transmit PLL Control Register
09h
6
TPLLOFS0
0
0
5
PLLOS
0
0
4
TPLLIFS0
0
0
3
TPLLIFS1
0
0
2
TPLLSS
0
0
1
TCSS1
0
TCSS1
PIN 31
0
TCSS0
0
TCSS0
PIN 63
For more information on all the bits in the Transmit PLL control register, refer to
Figure 3-3.
Bits 0 and 1: Transmit Clock (TX CLOCK) Source Select (TCSS[1:0]).
These bits control the output of the TX PLL
Clock Mux function. See
Figure 3-3.
TCSS1
0
0
1
1
TCSS0
0
1
0
1
Transmit Clock (TX CLOCK) Source
(See
Figure 3-3)
The TCLK pin is the source of transmit clock.
The PLL_CLK is the source of transmit clock.
The scaled signal present at MCLK as the transmit clock.
The signal present at RCLK is the transmit clock.
Bit 2: Transmit PLL_CLK Source Select (TPLLSS).
Selects the reference signal for the TX PLL.
0 = Use the recovered network clock. This is the same clock available at the RCLK pin (output).
1 = Use the externally provided clock present at the TCLK pin.
35 of 124

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