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DS26502数据手册封面

DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

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DS26502 T1/E1/J1/64KCC BITS Element
13.7 LIU Control Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
7
L2
0
L2
PIN 13
LIC1
Line Interface Control 1
30h
6
L1
0
L1
PIN 12
5
L0
0
L0
PIN 11
4
EGL
0
0
3
JAS
0
0
2
JABDS
0
0
1
DJA
0
0
0
TPD
0
1
Bit 0: Transmit Power-Down (TPD)
0 = powers down the transmitter and tri-states the TTIP and TRING pins
1 = normal transmitter operation
Bit 1: Disable Jitter Attenuator (DJA). Note:
The jitter attenuator is only available in T1 and E1 modes.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Bit 2/Jitter Attenuator Buffer Depth Select (JABDS). Note:
The jitter attenuator is only available in T1 and E1 modes.
0 = 128 bits
1 = 32 bits (use for delay-sensitive applications)
Bit 3: Jitter Attenuator Select (JAS). Note:
The jitter attenuator is only available in T1 and E1 modes.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Bit 4: Receive Equalizer Gain Limit (EGL).
This bit controls the sensitivity of the receive equalizer.
T1 Mode: 0 = -36dB (long haul)
1 = -15dB (limited long haul)
E1 Mode: 0 = -43dB (long haul)
1 = -12dB (short haul)
Bits 5 to 7: Line Build-Out Select (L0 to L2).
When using the internal termination, the user needs only to select 000 for 75鈩?/div>
operation or 001 for 120鈩?operation. This selects the proper voltage levels for 75鈩?or 120鈩?operation. Using TT0 and TT1 of
the LICR4 register, users can then select the proper internal source termination. Line build-outs 100 and 101 are for backwards
compatibility with older products only.
E1 Mode
L2
L1
0
0
0
0
1
0
1
0
L0
0
1
0
1
APPLICATION
75鈩?normal
120鈩?normal
75鈩?with high return loss*
120鈩?with high return loss*
N (1)
1:2
1:2
1:2
1:2
RETURN LOSS
N.M.
N.M.
21dB
21dB
Rt (1)
0
0
6.2鈩?/div>
11.6鈩?/div>
*TT0
and TT1 of LIC4 register must be set to zero in this configuration.
81 of 124

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