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DS26502数据手册封面

DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

  • 1043.62KB

  • 125页

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DS26502 T1/E1/J1/64KCC BITS Element
7.3.1 Power-Up Sequence
The DS26502 contains an on-chip power-up reset function, which automatically clears the writeable
register space immediately after power is supplied to the device. The user can issue a chip reset at any
time. Issuing a reset will disrupt signals flowing through the DS26502 until the device is reprogrammed.
The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST
function in the master mode register. The LIRST (LIC2.6) should be toggled from zero to one to reset the
line interface circuitry. (It will take the DS26502 about 40ms to recover from the LIRST bit being
toggled.)
7.3.2 Test Reset Register
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
7
鈥?/div>
0
X
TSTRREG
Test Reset Register
00h
6
鈥?/div>
0
X
5
TEST1
0
X
4
TEST0
0
X
3
鈥?/div>
0
X
2
鈥?/div>
0
X
1
鈥?/div>
0
X
0
SFTRST
0
X
Bit 0: Software Issued Reset (SFTRST).
A zero-to-one transition causes the register space in the DS26502 to be cleared. A
reset clears all configuration and status registers. The bit automatically clears itself when the reset has completed.
Bits 1 to 3: Unused, must be set = 0 for proper operation.
Bits 4 and 5: Test Mode Bits (TEST0, TEST1).
Test modes are used to force the output pins of the DS26502 into known
states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from
shared buses.
TEST1
0
0
1
1
TEST0
0
1
0
1
Effect On Output Pins
Operate normally
Force all output pins into tri-state (including all I/O pins and parallel port pins)
Force all output pins low (including all I/O pins except parallel port pins)
Force all output pins high (including all I/O pins except parallel port pins)
Bits 6 and 7: Unused, must be set = 0 for proper operation.
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