DS26502 T1/E1/J1/64KCC BITS Element
Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only)
CLOCK
JITTER
ATTENUATOR
ENABLED AND
IN RX PATH
RCLK
FROM RX
LIU
+ DATA
+ DATA
TO RX
FRAMER
- DATA
- DATA
LOCAL
LOOPBACK
(LBCR.3)
TX CLOCK
JITTER
ATTENUATOR
ENABLED AND
IN TX PATH
CLOCK
TO TX
LIU
+ DATA
+ DATA
FROM TX
FORMATTER
- DATA
REMOTE
LOOPBACK
(LBCR.4)
- DATA
Figure 3-3. Transmit PLL Clock Mux Diagram
TPCR.3
TPCR.4
TPCR.2
IN
SEL
TPCR.6
TPCR.7
OUT
SEL
TPCR.5
PLL_OUT PIN
RECOVERED CLOCK
TCLK PIN
TX PLL
OUTPUT = 1.544MHz,
2.048MHz, 64kHz,
6.312MHz
TX CLOCK
JA CLOCK
TPCR.0
(TCSS0)
(HARDWARE MODE PIN NAME)
TPCR.1
(TCSS1)
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