DS26502 T1/E1/J1/64KCC BITS Element
TABLE OF CONTENTS
1.
1.1
1.2
1.3
1.4
1.5
1.6
2.
3.
4.
4.1
4.2
4.3
4.4
4.5
4.6
4.7
5.
6.
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7.
FEATURES......................................................................................................................7
G
ENERAL
........................................................................................................................7
L
INE
I
NTERFACE
...............................................................................................................7
J
ITTER
A
TTENUATOR
(T1/E1 M
ODES
O
NLY
) ......................................................................7
F
RAMER
/F
ORMATTER
.......................................................................................................8
T
EST AND
D
IAGNOSTICS
...................................................................................................8
C
ONTROL
P
ORT
...............................................................................................................8
SPECIFICATIONS COMPLIANCE ...................................................................................9
BLOCK DIAGRAMS .......................................................................................................11
PIN FUNCTION DESCRIPTION .....................................................................................14
T
RANSMIT
PLL...............................................................................................................14
T
RANSMIT
S
IDE
..............................................................................................................14
R
ECEIVE
S
IDE
................................................................................................................15
C
ONTROLLER
I
NTERFACE
................................................................................................16
JTAG ...........................................................................................................................20
L
INE
I
NTERFACE
.............................................................................................................20
P
OWER
.........................................................................................................................21
PINOUT...........................................................................................................................22
HARDWARE CONTROLLER INTERFACE....................................................................25
T
RANSMIT
C
LOCK
S
OURCE
.............................................................................................25
I
NTERNAL
T
ERMINATION
..................................................................................................25
L
INE
B
UILD
-O
UT
.............................................................................................................26
R
ECEIVER
O
PERATING
M
ODES
........................................................................................26
T
RANSMITTER
O
PERATING
M
ODES
..................................................................................27
MCLK P
RE
-S
CALER
......................................................................................................27
O
THER
H
ARDWARE
C
ONTROLLER
M
ODE
F
EATURES
.........................................................28
PROCESSOR INTERFACE ............................................................................................29
7.1
P
ARALLEL
P
ORT
F
UNCTIONAL
D
ESCRIPTION
.....................................................................29
7.2
SPI S
ERIAL
P
ORT
I
NTERFACE
F
UNCTIONAL
D
ESCRIPTION
.................................................29
7.2.1 Clock Phase and Polarity .........................................................................................29
7.2.2 Bit Order...................................................................................................................29
7.2.3 Control Byte .............................................................................................................29
7.2.4 Burst Mode...............................................................................................................29
7.2.5 Register Writes.........................................................................................................30
7.2.6 Register Reads ........................................................................................................30
7.3
R
EGISTER
M
AP
..............................................................................................................31
7.3.1 Power-Up Sequence ................................................................................................33
7.3.2 Test Reset Register .................................................................................................33
7.3.3 Mode Configuration Register....................................................................................34
7.4
I
NTERRUPT
H
ANDLING
....................................................................................................37
7.5
S
TATUS
R
EGISTERS
.......................................................................................................37
7.6
I
NFORMATION
R
EGISTERS
...............................................................................................38
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