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DS26502数据手册封面

DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

  • 1043.62KB

  • 125页

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DS26502 T1/E1/J1/64KCC BITS Element
Table 9-2. E1 Alarm Criteria
ALARM
RLOF
SET CRITERIA
An
RLOF
condition exists on power-up
prior to initial synchronization, when a
resync criteria has been met, or when a
manual resync has been initiated via
E1RCR.0
255 or 2048 consecutive zeros received as
determined by E1RCR.0
Bit 3 of non-align frame set to one for
three consecutive occasions
Fewer than three zeros in two frames (512
bits)
Bit 6 of time slot 16 in frame 0 has been
set for two consecutive multiframes
Two out of three Sa7 bits are zero
CLEAR CRITERIA
ITU
SPEC.
RLOS
RRA
RUA1
RDMA
V52LNK
In 255-bit times, at least 32
ones are received
Bit 3 of non-align frame set to
zero for three consecutive
occasions
More than two zeros in two
frames (512 bits)
G.775/G.962
O.162
2.1.4
O.162
1.6.1.2
G.965
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
7
ID7
0
X
IDR
Device Identification Register
10h
6
ID6
0
X
5
ID5
0
X
4
ID4
0
X
3
ID3
N
X
2
ID2
N
X
1
ID1
N
X
0
ID0
N
X
Bits 0 to 3: Chip Revision Bits (ID0 to ID3).
The lower four bits of the IDR are used to display the die revision of the chip.
IDO is the LSB of a decimal code that represents the chip revision.
Bits 4 to 7: Device ID (ID4 to ID7).
The upper four bits of the IDR are used to display the DS26502 ID. The DS26502 ID is
0000.
48 of 124

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