DS26502 Datasheet

IC型号：
DS26502
PDF描述：
T1/E1/J1/64KCC BITS单元
文件大小：
1043.62KB
PDF页数：
125页
芯片厂家：
MAXIM

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DS26502 T1/E1/J1/64KCC BITS Element

1. FEATURES

1.1 General

搂

64-pin, 10mm x 10mm LQFP package

3.3V supply with 5V-tolerant inputs and outputs

Evaluation kits

IEEE 1149.1 JTAG Boundary Scan

Driver source code available from the factory

1.2 Line Interface

Requires a single master clock (MCLK) for E1, T1, or J1 operation. Master clock can be

2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz,

6.176MHz, or 12.352MHz for T1-only operation.

Fully software configurable

Short- and long-haul applications

Automatic receive sensitivity adjustments

Ranges include 0dB to -43dB or 0dB to -12dB for E1 applications; 0dB to -36dB or 0dB to -15dB

for T1 applications

Receive level indication in 2.5dB steps from -42.5dB to -2.5dB

Internal receive termination option for 75鈩? 100鈩? 110鈩? and 120鈩?lines

Monitor application gain settings of 20dB, 26dB, and 32dB

G.703 receive-synchronization signal mode

Flexible transmit-waveform generation

T1 DSX-1 line build-outs

E1 waveforms include G.703 waveshapes for both 75鈩?coax and 120鈩?twisted cables

AIS generation independent of loopbacks

Alternating ones and zeros generation

Square-wave output

Open-drain output option

Transmitter power-down

Transmitter 50mA short-circuit limiter with exceeded indication of current limit

Transmit open-circuit-detected indication

1.3 Jitter Attenuator (T1/E1 Modes Only)

32-bit or 128-bit crystal-less jitter attenuator

Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use

1.544MHz for T1 operation

Can be placed in either the receive or transmit path or disabled

Limit trip indication

7 of 124

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