DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

  • 1043.62KB

  • 125页

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DS26502 T1/E1/J1/64KCC BITS Element
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
7
鈥?/div>
0
X
SR1
Status Register 1
14h
6
鈥?/div>
0
X
5
鈥?/div>
0
X
4
JALT
0
X
3
鈥?/div>
0
X
2
TCLE
0
X
1
TOCD
0
X
0
鈥?/div>
0
X
Bits 0, 3, 5 to 7: Unused, must be set = 0 for proper operation.
Bit 1: Transmit Open Circuit Detect Condition (TOCD).
Set when the device detects that the TTIP and TRING outputs are
open-circuited.
Note:
This function not supported in transmit 6312kHz mode.
Bit 2: Transmit Current Limit Exceeded Condition (TCLE).
Set when the 50mA (rms) current limiter is activated whether
the current limiter is enabled or not.
Note:
This function not supported in transmit CMI, 64kHz or 6312kHz mode.
Bit 4: Jitter Attenuator Limit Trip Event (JALT).
Set when the jitter attenuator FIFO reaches to within 4 bits of its useful
limit. Will be cleared when read. Useful for debugging jitter-attenuation operation.
Note:
The jitter attenuator is only available
in T1 and E1 modes.
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