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DS26502 Datasheet

  • DS26502

  • T1/E1/J1/64KCC BITS单元

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  • 125页

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DS26502 T1/E1/J1/64KCC BITS Element
16. 6312kHz SYNCHRONIZATION INTERFACE
The DS26502 has a 6312kHz Synchronization Interface mode of operation that conforms with Appendix
II.2 of G.703, with the exception that the DS26502 transmits a square wave as opposed to the sine wave
that is defined in the G.703 specification.
16.1 Receive 6312kHz Synchronization Interface Operation
On the receive interface, a 6312kHz sine wave is accepted conforming to the input port requirements of
G.703 Appendix II. Alternatively, a 6312kHz square wave will also be accepted. A 6312kHz square wave
is output on RCLK in the receive direction. RS_8K and 400Hz are not driven in this mode and will be tri-
stated.
Table 16-1. Specification of 6312kHz Clock
Signal at Input Port
Frequency
Signal format
Alarm condition
6312kHz
Sinusoidal wave
Alarm should not be occurred against
the amplitude ranged
-16dBm to +3dBm
16.2 Transmit 6312kHz Synchronization Interface Operation
On the transmit interface, a nominally 50% duty cycle, 6312kHz square wave at standard logic levels is
available from the PLL_OUT pin. In normal operation, the TCLKO pin will output the same signal.
However, if remote loopback is enabled then TCLKO will be replaced with the recovered receive clock.
See
Figure 3-1.
The G.703 requirements for the 6312kHz transmitted signal are shown in
Table 16-2.
The
user must provide an external circuit to convert the TCLKO or PLL_OUT signal to the level and
impedance required by G.703. The RSER and TS_8K-4 pins are ignored in this mode. TTIP and TRING
will be tri-stated in this mode.
Table 16-2. Specification of 6312kHz Clock
Signal at Output Port
Frequency
Load impedance
Transmission media
Amplitude
6312kHz
75W resistive
Coaxial pair cable
0dBm
卤
3dBm
97 of 124

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