TMS320C2811 Datasheet

IC型号：
TMS320C2811
PDF描述：
具有片内 ROM 的 32 位数字信号控制器
文件大小：
2601.82KB
PDF页数：
162页
芯片厂家：
TI

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TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B 鈥?APRIL 2001 鈥?REVISED SEPTEMBER 2001

peripheral frames 0, 1, 2 (PFn)

The F2810 and F2812 segregate peripherals into three sections. The mapping of peripherals is as follows:

PF0:

XINTF:

PIE:

Flash:

Timers:

CSM:

PF1:

PF2:

eCAN:

SYS:

GPIO:

EV:

McBSP:

SCI:

SPI:

External Interface Configuration Registers

PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash Control, Programming, Erase, Verify Registers

CPU-Timers 0, 1, 2 Registers

Code Security Module KEY Registers

eCAN Mailbox and Control Registers

System Control Registers

GPIO Mux Configuration and Control Registers

Event Manager (EVA/EVB) Control Registers

McBSP Control and TX/RX Registers

Serial Communications Interface (SCI) Control and RX/TX Registers

Serial Peripheral Interface (SPI) Control and RX/TX Registers

12-Bit ADC Registers

PRODUCT PREVIEW

ADC:

general-purpose input/output (GPIO) multiplexer

Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user

to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured as

inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For specific

inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches.

32-bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The

timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The

counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter

reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timers 1 and 2 are reserved for

Real-Time OS (RTOS) applications. CPU-Timer 2 is connected to INT14 of the CPU. CPU-Timer 1 can be

connected to INT13 of the CPU. CPU-Timer 0 is for general use and is connected to the PIE block.

motor control peripherals

The F2810 and F2812 support the following peripherals which, are used for controlling motors:

EV:

The event manager module includes general-purpose timers, full-compare/PWM units,

capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event

managers are provided which enable two three-phase motors to be driven or four two-phase

motors. The event managers on the F2810 and F2812 are compatible to the event managers

on the 240x devices (with some minor enhancements).

The ADC block is a 12-bit converter, single ended, 16-channels. It will contain two

sample-and-hold units for simultaneous sampling.

ADC:

POST OFFICE BOX 1443

鈥?/div>

HOUSTON, TEXAS 77251鈥?443

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