TMS320C2811 Datasheet

IC型号：
TMS320C2811
PDF描述：
具有片内 ROM 的 32 位数字信号控制器
文件大小：
2601.82KB
PDF页数：
162页
芯片厂家：
TI

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TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B 鈥?APRIL 2001 鈥?REVISED SEPTEMBER 2001

vector table mapping

The interrupt vector table can be mapped into the five distinct areas listed in Table 19.

Table 19. Interrupt Vector Table Mapping

鈥?/div>

VECTOR MAPS

M1 Vector鈥?/div>

M0 Vector

BROM Vector

XINTF Vector搂

PIE Vector

VECTORS FETCHED

FROM

M1 SARAM Block

M0 SARAM Block

ROM Block

XINTF Zone 7 Block

PIE Block

ADDRESS RANGE

0x000000鈥?x00003F

0x3FFFC0鈥?x3FFFFF

0x000D00鈥?x000DFF

VMAP

M0M1MAP

MP/MC

ENPIE

鈥?On the F2810 and F2812 devices, the VMAP and M0M1MAP modes are set to 鈥?鈥?on reset. The ENPIE mode is forced to 鈥?鈥?on reset.

鈥?Vector map M1 Vector is a reserved mode only.

搂 Valid on F2812 only

After reset operation, the vector table will be located in the areas listed in Table 20.

PRODUCT PREVIEW

Table 20. Vector Table Mapping After Reset Operation

鈥?/div>

VECTOR MAPS

BROM Vector

XINTF Vector搂

RESET FETCHED

FROM

ROM Block

XINTF Zone 7 Block

ADDRESS RANGE

0x3FFFC0鈥?x3FFFFF

VMAP

M0M1MAP

MP/MC

ENPIE

鈥?On the F2810 and F2812 devices, the VMAP and M0M1MAP modes are set to 鈥?鈥?on reset. The ENPIE mode is forced to 鈥?鈥?on reset.

搂 Valid on F2812 only

The vector mapping is controlled by the following mode bits/signals:

VMAP:

This bit is found in Status Register 1 (bit 3). A device reset sets this bit to 1. The state of this

bit can be modified by writing to ST1 or by 鈥淪ETC/CLRC VMAP鈥?instructions.

This bit is found in Status Register 1 (bit 11). A device reset sets this bit to 1. The state of this

bit can be modified by writing to ST1 or by 鈥淪ETC/CLRC M0M1MAP鈥?instructions. This bit

should remain set. M0M1MAP = 0 is reserved for TI testing.

This bit is found in XINTCNF2 Register (bit 8). On the F2812, the default value of this bit, on

reset, is set by the XMP/MC input device signal. On the F2810, XMP/MC is tied low internally.

The state of this bit can be modified by writing to the XINTCNF2 register (address 0x0000

0B34).

This bit is found in PIECTRL Register (bit 0). The default value of this bit, on reset, is set to 鈥?鈥?/div>

(PIE disabled). The state of this bit can be modified by writing to the PIECTRL register

(address 0x0000 0CE0).

M0M1MAP:

MP/MC:

ENPIE:

The external interrupts are configured using the registers listed in Table 27.

POST OFFICE BOX 1443

鈥?/div>

HOUSTON, TEXAS 77251鈥?443

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