Table 48. TIMERxTCR Register Bit Definitions
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BIT
15
NAME
TIF
R/W
R/W=1
RESET
0
DESCRIPTION
Timer Interrupt Flag. This flag gets set when the timer decrements to zero. This bit can be
cleared by software writing a 1, but it can only be set by the timer reaching zero. Writing a 1
to this bit will clear it, writing a zero has no effect.
Timer Interrupt Enable. If the timer decrements to zero, and this bit is set, the timer will assert
its interrupt request.
Reserved
Timer Emulation Modes: These bits are special emulation bits that determine the state of
the timer when a breakpoint is encountered in the high-level language debugger. If the
FREE bit is set to 1, then, upon a software breakpoint, the timer continues to run (that is,
free runs). In this case, SOFT is a
don鈥檛 care.
But if FREE is 0, then SOFT takes effect. In
this case, if SOFT = 0, the timer halts the next time the TIMH:TIM decrements. If the SOFT
bit is 1, then the timer halts when the TIMH:TIM has decremented to zero.
FREE
10
SOFT
R/W
0
0
0
1
1
Note:
9:6
5
Reserved
TRB
R/W
W/R=0
0
0
0
1
0
1
Stop after the next decrement of the TIMH:TIM (hard stop)
Stop after the TIMH:TIM decrements to 0 (soft stop)
Free run
Free run
SOFT
Timer Emulation Mode
14
13:12
11
TIE
Reserved
FREE
R/W
R
R/W
0
0
0
That in the SOFT STOP mode, the timer will generate an interrupt before
shutting down (since reaching 0 is the interrupt causing condition).
Reserved
Timer Reload bit. When you write a 1 to TRB, the TIMH:TIM is loaded with the value in the
PRDH:PRD, and the prescaler counter (PSCH:PSC) is loaded with the value in the timer
divide-down register (TDDRH:TDDR). The TRB bit is always read as zero.
Timer stop status bit. TSS is a 1-bit flag that stops or starts the timer. To stop the timer, set
TSS to 1. To start or restart the timer, set TSS to 0. At reset, TSS is cleared to 0 and the timer
immediately starts.
Reserved
4
TSS
R/W
0
3:0
Reserved
鈥?x = 0, 1, or 2
R/W
0
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鈥?/div>
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