TMS320C2811 Datasheet

IC型号：
TMS320C2811
PDF描述：
具有片内 ROM 的 32 位数字信号控制器
文件大小：
2601.82KB
PDF页数：
162页
芯片厂家：
TI

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TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B 鈥?APRIL 2001 鈥?REVISED SEPTEMBER 2001

enhanced analog-to-digital converter (ADC) module (continued)

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,

traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize

switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation

techniques must be used to isolate the ADC module power pins (such as V

CCA

, V

REFHI

, and V

SSA

) from the

digital supply.

Notes:

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is

controlled by the high-speed peripheral clock (HSPCLK).

2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:

ADCENCLK:

On reset, this signal will be low. While reset is active-low (XRS) the clock to the register will still

function. This is necessary to make sure all registers and modes go into their default reset state. The analog

module will however be in a low-power inactive state. As soon as reset goes high, then the clock to the

registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers

will be enabled and the analog module will be enabled. There will be a certain time delay (ms range) before

the ADC is stable and can be used.

HALT:

This signal only affects the analog module. It does not affect the registers. If low, the ADC module is

powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the CPU,

which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.

POST OFFICE BOX 1443

鈥?/div>

HOUSTON, TEXAS 77251鈥?443

PRODUCT PREVIEW

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