TMS320C2811 Datasheet

IC型号：
TMS320C2811
PDF描述：
具有片内 ROM 的 32 位数字信号控制器
文件大小：
2601.82KB
PDF页数：
162页
芯片厂家：
TI

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TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B 鈥?APRIL 2001 鈥?REVISED SEPTEMBER 2001

XINTCNF2 register

Table 15. XINTCNF2 Register Bit Definitions

BITS

1,0

TYPE

R/W

NAME

Write

Buffer

Depth

RESET

0,0

DESCRIPTION

The write buffer allows the processor to continue execution without waiting for

XINTF write accesses to complete. The write buffer depth is selectable as follows:

Depth

Action

No write buffering. The CPU will be stalled until the write

completes on the XINTF.

Note:

Default mode on reset (XRS).

The XINTF will buffer one word. The CPU is stalled until the

write cycle begins on the XINTF (there could be a read cycle

currently active on the XINTF).

One write will be buffered without stalling the CPU. The CPU

is stalled if a second write follows. The CPU will be stalled

until the first write begins its cycle on the XINTF.

Two writes will be buffered without stalling the CPU. The CPU

is stalled if a third write follows. The CPU will be stalled until

the first write begins its cycle on the XINTF.

The buffered access can be 8, 16, or 32 bits in length. Order of execution is

preserved, e.g., writes are performed in the order they were accepted. The

processor is stalled on XINTF reads until all pending writes are done and the read

access completes. If the buffer is full, any pending reads or writes to the buffer

will stall the processor.

The 鈥淲rite Buffer Depth鈥?can be changed; however, it is recommended that the

write buffer depth be changed only when the buffer is empty (this can be checked

by reading the 鈥淲rite Buffer Level鈥?bits). Writing to these bits when the level is not

zero may have unpredictable results.

R/W

CLKMODE

Mode

XCLKOUT divide by 2 mode. If this bit is set to 1, XCLKOUT is a divide by 2 of

XTIMCLK. If this bit is set to 0, XCLKOUT is equal to XTIMCLK. All bus timings,

irrespective of which mode is enabled, will start from the rising edge of XCLKOUT.

The default mode of operation on power up and reset is /2 mode.

Turn XCLKOUT off mode. When this bit is set to 1, the XCLKOUT signal is turned

off. This is done for power savings and noise reduction. This bit is set to 0 on a

reset.

Reserved

R/W

CLKOFF

Reserved

POST OFFICE BOX 1443

鈥?/div>

HOUSTON, TEXAS 77251鈥?443

PRODUCT PREVIEW

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