TMS320C2811 Datasheet

  • TMS320C2811

  • 具有片内 ROM 的 32 位数字信号控制器

  • 2601.82KB

  • 162页

  • TI

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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B 鈥?APRIL 2001 鈥?REVISED SEPTEMBER 2001
enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 15. The ADC module consists of
a 12-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include:
D
12-bit ADC core with built-in S/H
D
Analog input: 0 V to 2.5 V
D
Fast conversion time:
鈥?/div>
鈥?/div>
Single conversion time: 200 ns
Pipelined conversion time: 60 ns
D
16-channel, muxed inputs
D
Autosequencing capability provides up to 16 鈥渁utoconversions鈥?in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
D
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
鈥?/div>
The digital value of the input analog voltage is derived by:
Digital Value
+
4095
Input Analog Voltage
*
ADCLO
2.5
D
Multiple triggers as sources for the start-of-conversion (SOC) sequence
鈥?/div>
鈥?/div>
鈥?/div>
S/W 鈥?software immediate start
EVA 鈥?Event manager A (multiple event sources within EVA)
EVB 鈥?Event manager B (multiple event sources within EVB)
D
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
D
Sequencer can operate in 鈥渟tart/stop鈥?mode, allowing multiple 鈥渢ime-sequenced triggers鈥?to synchronize
conversions
D
EVA and EVB triggers can operate independently in dual-sequencer mode
D
Sample-and-hold (S/H) acquisition time window has separate prescale control
D
Calibration mode
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
67
PRODUCT PREVIEW
D
Sixteen result registers (individually addressable) to store conversion values

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