RESET鈥?/div>
0,0
1:1
DESCRIPTION
These bits set the low power mode for the device.
Select number of OSCCLK clock cycles to qualify the selected inputs when
waking the LPM from STANDBY mode:
000000 = 2 OSCCLKs
000001 = 3 OSCCLKs
.
111111 = 65 OSCCLKs
15:8
reserved
R=0
0:0
鈥?These bits are cleared by a reset (XRS).
鈥?The low power mode bits (LPM) are only valid when the IDLE instruction is executed. Therefore, the user must set the LPM bits to the appropriate
mode before executing the IDLE instruction.
Table 42. LPMCR1 Register Bit Definitions
BIT(S)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NAME
XINT1
XNMI
WDINT
T1CTRIP
T2CTRIP
T3CTRIP
T4CTRIP
C1TRIP
C2TRIP
C3TRIP
C4TRIP
C5TRIP
C6TRIP
SCIRXA
SCIRXB
CANRX
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET鈥?/div>
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
If the res ective bit is set to 1, it will enable the selected signal to wake the
respective
device from STANDBY mode. If the bit is cleared, the signal will have no effect.
DESCRIPTION
鈥?These bits are cleared by a reset (XRS).
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
55
PRODUCT PREVIEW
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