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TMS320C2811 Datasheet

  • TMS320C2811

  • 具有片内 ROM 的 32 位数字信号控制器

  • 2601.82KB

  • 162页

  • TI

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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B 鈥?APRIL 2001 鈥?REVISED SEPTEMBER 2001
PIE registers (continued)
Table 23. PIECTRL Register Bit Definitions
BIT(S)
0
NAME
ENPIE
TYPE
R/W
RESET
0
DESCRIPTION
Enable vector fetching from PIE block. When this bit is set to 1, all vectors are fetched from
the PIE vector table. If this bit is set to 0, the PIE block is disabled and vectors are fetched
as normal. All PIE block registers (PIEACK, PIEIFR, PIEIER) can be accessed even when
the PIE block is disabled.
Vector fetch address. Displays the address of the vector that was fetched. The least
significant bit of the address is ignored and only bits 1 to 15 are shown. The vector address
can be used to determine which interrupt generated the fetch.
15:1
PIEVECT
R
0
Table 24. PIEACK Register Bit Definitions
BIT(S)
11:0
NAME
PIEACK
TYPE
R/W=1
RESET
0
DESCRIPTION
Writing a 1 to the respective interrupt bit enables the PIE block to drive a pulse into the CPU
interrupts input, if an interrupt is pending on any of the group interrupts. Reading this
register indicates if an interrupt is pending in the respective group. Bit 0 refers to INT1 up
to Bit 11, which refers to INT12.
Note:
15:12
spares
R=0
0
Writes of 0 are ignored.
PRODUCT PREVIEW
Table 25. PIEIERx Register Bit Definitions
鈥?/div>
BIT(S)
0
1
2
3
4
5
6
7
NAME
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
0
0
0
0
0
0
0
0
These register bits individually enable an interrupt within a group. They behave very much
group
like the CPU interru t enable register. Setting a bit to 1 will enable the servicing of the
interrupt
respective interrupt. Setting a bit to 0 will disable the servicing of the bit.
DESCRIPTION
15:8
spares
R=0
0
鈥?x = 1 to 12. INTx means CPU interrupts INT1 to INT12.
Table 26. PIEIFRx Register Bit Definitions
鈥?/div>
BIT(S)
0
1
2
3
4
5
6
7
15:8
NAME
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
spares
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R=0
RESET
0
0
0
0
0
0
0
0
0
Note:
The PIEIFR register bit is cleared during the interrupt vector fetch portion of
the interrupt processing.
These register bits indicate if an interrupt is currently active. They behave very much like
the
th CPU i t
interrupt fl register. Wh an i t
t flag
i t When interrupt i active, th respective register bit i set.
t is ti
the
ti
i t
is t
The bit is cleared when the interrupt is serviced or by writing a 0 to the register bit. This
bit
register can also be read to determine which interru ts are active or pending.
interrupts
ending.
DESCRIPTION
鈥?x = 1 to 12. INTx means CPU interrupts INT1 to INT12.
40
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443

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