TMS320C2811 Datasheet

IC型号：
TMS320C2811
PDF描述：
具有片内 ROM 的 32 位数字信号控制器
文件大小：
2601.82KB
PDF页数：
162页
芯片厂家：
TI

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TMS320F2810, TMS320F2812

DIGITAL SIGNAL PROCESSORS

SPRS174B 鈥?APRIL 2001 鈥?REVISED SEPTEMBER 2001

XINTCNF2 register (continued)

Table 15. XINTCNF2 Register Bit Definitions (Continued)

BITS

7,6

TYPE

NAME

WLEVEL

RESET

0,0

DESCRIPTION

The current number of writes buffered are detectable as follows:

Level

Action

empty

1 value currently in the write buffer

2 values currently in the write buffer

3 values currently in the write buffer

The value in the write buffer may be 8-, 16-, or 32-bit data.

Note:

There may be a few cycle delay from when a value enters the write buffer

to the buffer level depth being updated.

R/W

MP/MC

Mode

On reset, this bit reflects the state of the XMP/MC input signal sampled at XRS.

The user can modify the state of this bit by writing a 1 or a 0 to this location. This

will be reflected on the XMP/MC output signal. This mode also affects ZONE 7 and

Boot ROM mapping as follows:

MP/MC = 1, microprocessor state

(XINTF ZONE 7 enabled, Boot ROM disabled).

MP/MC = 0, microcomputer state

(XINTF ZONE 7 disabled, Boot ROM enabled).

Note:

The XMP/MC input signal state is ignored after reset.

R/W

HOLD

This bit, when low, will automatically grant a request to an external device driving

the XHOLD input signal low (XHOLDA output signal is driven low when request

granted). This bit, when set high, will not automatically grant a request to an

external device driving the XHOLD input signal low (XHOLDA output signal stays

high).

If this bit is set, while XHOLD and XHOLDA are both low (external bus accesses

granted) then the XHOLDA signal is forced high (at the end of the current cycle)

and the exteranl interface is taken out of high-impedance mode.

On a reset XRS, this bit is set to zero. If on a reset the XHOLD signal is active-low,

then the bus and all signal strobes must be in high-impedance state and the

XHOLDA signal also driven active-low.

When HOLD mode is enabled and XHOLDA is active-low (external bus grant

active) then the core can still execute code from internal memory. If an access is

made to the external interface, then a not ready signal is generated and the core

is stalled until the XHOLD signal is removed.

HOLDS

XHOLD input

signal

XHOLDA input

signal

This bit reflects the current state of the XHOLD input signal. It can be read by the

user to determine if an external device is requesting access to the external bus.

This bit reflects the current state of the XHOLDA output signal. It can be read by

the user to determine if the external interface is currently granting access to an

external device.

PRODUCT PREVIEW

HOLDAS

POST OFFICE BOX 1443

鈥?/div>

HOUSTON, TEXAS 77251鈥?443

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