您的位置：维库电子市场网 > Datasheet > MSC8101
MSC8101数据手册封面

MSC8101 Datasheet

  • MSC8101

  • Networking Digital Signal Processor

  • 1873.07KB

  • Motorola   Motorola

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

Signals/Connections
Table 1-4.
Signal Name
BTM[0鈥?]
Reset, Configuration, and EOnCE Event Signals (Continued)
Signal Description
Boot Mode 0鈥?
Determines the MSC8101 boot mode when PORESET is deasserted. See the emulation and debug
chapter in the
SC140 DSP Core Reference Manual
for details on how to set these pins.
EOnCE Event 4
After PORESET is deasserted, you can configure EE4 as an input (default) or an output. See the
emulation and debug chapter in the
SC140 DSP Core Reference Manual
for details on the ETRSMT
Register.
Type
Input
EE4
1
Input
Output
EE5
1
Enable Address Event Detection Channel 4 or generate an EOnCE event.
The DSP wrote the EOnCE Transmit Register (ETRSMT). Triggers external debugging equipment.
EOnCE Event 5
After PORESET is deasserted, you can configure EE5 as an input (default) or an output.
Input
Output
EED
1
Enable Address Event Detection Channel 5.
Detection by Address Event Detection Channel 5. Triggers external debugging equipment.
Enhanced OnCE (EOnCE) Event Detection
After PORESET is deasserted, you can configure EED as an input (default) or output:
Input
Output
PORESET
RSTCONF
Input
Input
Enable the Data Event Detection Channel.
Detection by the Data Event Detection Channel. Triggers external debugging equipment.
Power-On Reset
When asserted, this line causes the MSC8101 to enter power-on reset state.
Reset Configuration
Used during reset configuration sequence of the chip. A detailed explanation of its function is
provided in the 鈥淧ower-On Reset Flow鈥?and 鈥淗ardware Reset Configuration鈥?sections of the
MSC8101 Reference Manual.
Hard Reset
When asserted, this open-drain line causes the MSC8101 to enter the hard reset state.
Soft Reset
When asserted, this open-drain line causes the MSC8101 to enter the soft reset state.
HRESET
SRESET
Note:
Input
Input
See the emulation and debug chapter in the
SC140 DSP Core Reference Manual
for details on how to configure these pins.
1.4 System Bus, HDI16, and Interrupt Signals
The system bus, HDI16, and interrupt signals are grouped together because they use a common set of signal lines.
Individual assignment of a signal to a specific signal line is configured through registers in the System Interface
Unit (SIU) and the Host Interface (HDI16). 1-5 describes the signals in this group.
Note:
To boot from the host interface, the HDI16 must be enabled by pulling up the
HPE
signal line during
PORESET
. The configuration word must then be loaded from the host. The configuration word must set the
Internal Space Port Size bit in the Bus Control Register (BCR[ISPS]) to change the system data bus width
from 64 bits to 32 bits and reassign the upper 32 bits to their HDI16 functions. Never set the Host Port
Enable (HEN) bit in the Host Port Control Register (HPCR) to enable the HDI16, unless the bus size is
first changed from 64 bits to 32 bits. Otherwise, unpredictable operation may occur.
MSC8101 Technical Data, Rev. 16
1-6
Freescale Semiconductor

MSC8101 PDF文件相关型号

MSC8101D

MSC8101相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！