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MSC8101数据手册封面

MSC8101 Datasheet

  • MSC8101

  • Networking Digital Signal Processor

  • 1873.07KB

  • Motorola

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Signals/Connections
Table 1-7.
Name
General-
Purpose I/O
PA12
Port A Signals (Continued)
Peripheral Controller:
Dedicated Signal
Protocol
FCC1: RXD2
UTOPIA
Dedicated
I/O Data
Direction
Input
Description
FCC1: UTOPIA Receive Data Bit 2
The MSC8101 inputs ATM cell octets (UTOPIA interface data) on
RXD[0鈥?]. This is bit 2 of the receive data. RXD7 is the most significant
bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0鈥?] is
tri-stated, enabled only when RXENB is asserted.
Module Serial Number Bit 3
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0鈥?] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
FCC1: UTOPIA RX Receive Data Bit 1
The MSC8101 inputs ATM cell octets (UTOPIA interface data) on
RXD[0鈥?]. This is bit 1 of the receive data. RXD7 is the most significant
bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0鈥?] is
tri-stated, enabled only when RXENB is asserted.
Module Serial Number Bit 4
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0鈥?] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
FCC1: UTOPIA RX Receive Data Bit 0
The MSC8101 inputs ATM cell octets (UTOPIA interface data) on
RXD[0鈥?]. RXD0 is the least significant bit of the receive data. A cell is
53 bytes. To support Multi-PHY configurations, RXD[0鈥?] is tri-stated,
enabled only when RXENB is asserted.
Module Serial Number Bit 5
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0鈥?] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
SMC2: Serial Management Transmit Data
The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock.
Not all signals are used for all applications. SMCs are full-duplex ports
that supports three protocols or modes: UART, transparent, or general-
circuit interface (GCI). See also PC15.
Time-Division Multiplexing A1: Layer 1 Transmit Data Bit 0
L1TXD0 is the least significant bit of the TDM nibble data.
SMC2: Serial Management Receive Data
The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock.
Not all signals are used for all applications. SMCs are full-duplex ports
that supports three protocols or modes: UART, transparent, or general-
circuit interface (GCI).
Time-Division Multiplexing A1: Layer 1 Nibble Receive Data Bit 0
L1RXD0 is the least significant bit received in nibble mode.
Time-Division Multiplexing A1: Layer 1 Serial Receive Data
TDMA1 receives serial data from L1RXD.
SDMA: MSNUM3
Output
PA11
FCC1: RXD1
UTOPIA
Input
SDMA: MSNUM4
Output
PA10
FCC1: RXD0
UTOPIA
Input
SDMA: MSNUM5
Output
PA9
SMC2: SMTXD
Output
SI1 TDMA1: L1TXD0
TDM nibble
PA8
SMC2: SMRXD
Output
Input
SI1 TDMA1: L1RXD0
TDM nibble
SI1 TDMA1: L1RXD
TDM serial
Input
Input
MSC8101 Technical Data, Rev. 16
1-20
Freescale Semiconductor

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