MSC8101 Datasheet

  • MSC8101

  • Networking Digital Signal Processor

  • 1873.07KB

  • Motorola

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Clock Configuration
2.5.2.1 System Clock Control Register
Bit
Type
Reset
0
1
2
3
4
5
6
7
鈥?/div>
8
9
10
11
12
13
14
15
Reserved
鈥?/div>
Bit
Type
Reset
16
17
18
19
20
21
鈥?/div>
Reserved
鈥?/div>
22
23
24
25
26
27
CLKODIS
R/W
0
28
鈥?/div>
29
30
R/W
0
31
DFBRG
1
Reserved
鈥?/div>
Figure 2-1.
System Clock Control Register (SCCR)鈥?x10C80
SCCR is memory-mapped into the SIU register map of the MSC8101.
Table 2-7.
Name
Bit No.
鈥?/div>
0鈥?6
CLKODIS
27
SCCR Bit Descriptions
Description
Settings
Defaults
PORESET
鈥?/div>
0
Hard Reset
鈥?/div>
Unaffected
Reserved. Write to 0 fro future compatibility.
CLKOUT Disable
Disables the CLKOUT signal. The value of
CLKOUT when disabled is indeterminate (can be 1
or 0).
Reserved. Write to 0 fro future compatibility.
Division Factor for the BRG Clock
Defines the
BRGCLK frequency. Changing this value does not
result in a loss of lock condition.
00
01
10
11
Divide by 4
Divide by 16 (default value)
Divide by 64
Divide by 256
0
1
CLKOUT enabled (default)
CLKOUT disabled
鈥?/div>
28鈥?9
DFBRG
30鈥?1
鈥?/div>
01
鈥?/div>
Unaffected
2.5.2.2 System Clock Mode Register
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
COREPDF
Type
Reset
COREMF
R
鈥?/div>
BUSDF
CPMDF
Bit
16
17
18
19
20
21
22
23
24
鈥?/div>
R
鈥?/div>
25
DLLDIS
26
鈥?/div>
27
28
29
30
31
SPLLPDF
Type
Reset
SPLLMF
COREDF
Figure 2-2.
System Clock Mode Register (SCMR)鈥?x10C88
SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode control
signals to the PLLs, DLL, and clock logic. This register reflects the currently defined configuration settings. For
details of the available setting options, see
AN2306/D.
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
2-5

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