鈥?/div>
27
28
29
30
31
SPLLPDF
Type
Reset
SPLLMF
COREDF
Figure 2-2.
System Clock Mode Register (SCMR)鈥?x10C88
SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode control
signals to the PLLs, DLL, and clock logic. This register reflects the currently defined configuration settings. For
details of the available setting options, see
AN2306/D.
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
2-5