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MSC8101 Datasheet

  • MSC8101

  • Networking Digital Signal Processor

  • 1873.07KB

  • Motorola

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CPM Ports
Table 1-9.
Name
General-
Purpose I/O
PC22
Port C Signals (Continued)
Peripheral Controller:
Dedicated I/O
Protocol
SI1: L1ST1
Dedicated
I/O Data
Direction
Output
Description
Serial Interface 1: Layer 1 Strobe 1
The MSC8101 time-slot assigner supports up to four strobe outputs that
can be asserted on a bit or byte basis. The strobe outputs are useful for
interfacing to other devices that do not support the multiplexed interface or
for enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also generate output wave forms for such
applications as stepper-motor control.
Clock 10
The CPM supports up to 10 clock input pins sent to the bank-of-clocks
selection logic, where they can be routed to the controllers.
CLK10
Input
DMA: DREQ1
Input/ Output
DMA: Request 1
DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller.
DONE1 and DRACK1 are signals on the same pin and therefore cannot be
used simultaneously. There are two sets of DMA pins associated with the
PIO ports.
Output
SMC2: Serial Management Transmit Data
The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not
all signals are used for all applications. SMCs are full-duplex ports that
support three protocols or modes: UART, transparent, or general-circuit
interface (GCI). See also PA9.
SCC1: Clear To Send, Collision
Typically used in conjunction with RTS. The MSC8101 SCC1 transmitter
sends out a request to send data signal (RTS). The request is accepted
when CTS is returned low. CLSN is the signal used in Ethernet mode. See
also PC29.
FCC1: UTOPIA Master Transmit Address Bit 0
This is master transmit address bit 0.
FCC1: UTOPIA Slave Transmit Address Bit 0
This is slave transmit address bit 0.
Serial Interface 1: Layer 1 Strobe 2
The MSC8101 time-slot assigner supports up to four strobe outputs that
can be asserted on a bit or byte basis. The strobe outputs are useful for
interfacing to other devices that do not support the multiplexed interface or
for enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also be generate output wave forms for
such applications as stepper-motor control.
SCC1: Carrier Detect, Receive Enable
Typically used in conjunction with RTS supported by SCC1. The
MSC8101MSC8101 SCC1 transmitter requests the receiver to send data
by asserting RTS low. The request is accepted when CTS is returned low.
FCC1: UTOPIA Multi-PHY Master Receive Address Bit 0
This is master receive address bit 0.
FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 0
This is slave receive address bit 0.
PC15
SMC2: SMTXD
SCC1: CTS/CLSN
Input
FCC1: TXADDR0
UTOPIA master
FCC1: TXADDR0
UTOPIA slave
PC14
SI1: L1ST2
Output
Input
Output
SCC1: CD, RENA
Input
FCC1: RXADDR0
UTOPIA master
FCC1: RXADDR0
UTOPIA slave
Output
Input
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
1-29

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