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MSC8101数据手册封面

MSC8101 Datasheet

  • MSC8101

  • Networking Digital Signal Processor

  • 1873.07KB

  • Motorola

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Signals/Connections
Table 1-5.
Signal
D56
System Bus, HDI16, and Interrupt Signals (Continued)
Description
Data Bus Bit 56
In write transactions the bus master drives the valid data on this pin. In read transactions the slave
drives the valid data on this pin.
Host Acknowledge
3
When the HDI16 is programmed to interface with a single host request host bus, this pin is the host
acknowledge Schmitt trigger input (HACK). The polarity of the host acknowledge is programmable.
Receive Host Request
3
When the HDI16 is programmed to interface with a double host request host bus, this pin is the
receive host request output (HRRQ/HRRQ). The signal can be programmed as driven or open drain.
The polarity of the host request is programmable.
Data Bus Bit 57
In write transactions the bus master drives the valid data on this pin. In read transactions the slave
drives the valid data on this pin.
Host Data Strobe Polarity
3
When the HDI16 interface is enabled, this pin is the host data strobe polarity (HDSP).
Data Bus Bit 58
In write transactions the bus master drives the valid data on this pin. In read transactions the slave
drives the valid data on this pin.
Host Dual Data Strobe
3
When the HDI16 interface is enabled, this pin is the host dual data strobe (HDDS).
Data Bus Bit 59
In write transactions the bus master drives the valid data on this pin. In read transactions the slave
drives the valid data on this pin.
H8BIT
3
When the HDI16 interface is enabled, this bit determines if the interface is in 8-bit or 16-bit mode.
Data Bus Bit 60
In write transactions the bus master drives the valid data on this pin. In read transactions the slave
drives the valid data on this pin.
Host Chip Select
3
When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select
is a logical OR of HCS1 and HCS2.
Data Bus Bits 61鈥?3
Used only in 60x-mode-only mode. In write transactions the bus master drives the valid data on this
bus. In read transactions the slave drives the valid data on this bus.
These dedicated signals are reserved when the HDI16 is enabled.
3
Data Flow
Input/Output
HACK/HACK
Output
HRRQ/HRRQ
Output
D57
Input/Output
HDSP
D58
Input
Input/Output
HDDS
D59
Input
Input/Output
H8BIT
D60
Input
Input/Output
HCS2
Input
D[61鈥?3]
Input/Output
Reserved
Reserved
DP0
Input
Input/Output
The primary configuration is reserved.
Data Parity 0
1
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity zero pin should give odd parity (odd number of ones) on the group of signals that includes
data parity 0 and D[0鈥?].
External Bus Request 2
1,2
An external master asserts this pin to request bus ownership from the internal arbiter.
EXT_BR2
Input
MSC8101 Technical Data, Rev. 16
1-10
Freescale Semiconductor

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