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MSC8101数据手册封面

MSC8101 Datasheet

  • MSC8101

  • Networking Digital Signal Processor

  • 1873.07KB

  • Motorola

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CPM Ports
Table 1-9.
Name
General-
Purpose I/O
PC7
Port C Signals (Continued)
Peripheral Controller:
Dedicated I/O
Protocol
SI2: L1ST1
Dedicated
I/O Data
Direction
Output
Description
Serial Interface 2: Strobe 1
The MSC8101 time-slot assigner supports up to four strobe outputs that
can be asserted on a bit or byte basis. The strobe outputs are useful for
interfacing to other devices that do not support the multiplexed interface or
for enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also generate output wave forms for such
applications as stepper-motor control.
FCC1: Clear To Send
In the standard modem interface signals supported by FCC1 (RTS, CTS,
and CD). CTS is asynchronous with the data.
FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 2
This is master transmit address bit 2.
FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 2
This is slave transmit address bit 2.
FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 1 Direct
Polling
Asserted by an external UTOPIA slave PHY to indicate that it can accept
one complete ATM cell.
Serial Interface 2: Layer 1 Strobe 2
The MSC8101 time-slot assigner supports up to four strobe outputs that
can be asserted on a bit or byte basis. The strobe outputs are useful for
interfacing to other devices that do not support the multiplexed interface or
for enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also generate output wave forms for such
applications as stepper-motor control.
FCC1: Carrier Detect
In the standard modem interface signals supported by FCC1 (RTS, CTS,
and CD). CD is an input asynchronous with the data.
FCC1: UTOPIA Multi-PHY Master Receive Address Bit 2
This is master receive address bit 2.
FCC1: UTOPIA Slave Receive Address Bit 2
This is slave receive address bit 2.
FCC1: UTOPIA Multi-PHY Master Receive Cell Available 1 Direct
Polling
Asserted by an external PHY when one complete ATM cell is available for
transfer.
FCC1: CTS
HDLC serial, HDLC nibble,
and
transparent
FCC1: TXADDR2
UTOPIA master
FCC1: TXADDR2
UTOPIA slave
FCC1: TXCLAV1
UTOPIA multi-PHY master, direct
polling
PC6
SI2: L1ST2
Input
Output
Input
Input
Output
FCC1: CD
HDLC serial, HDLC nibble,
and
transparent
FCC1: RXADDR2
UTOPIA master
FCC1: RXADDR2
UTOPIA slave
FCC1: RXCLAV1
UTOPIA multi-PHY master, direct
polling
Input
Output
Input
Input
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
1-31

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