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MSC8101数据手册封面

MSC8101 Datasheet

  • MSC8101

  • Networking Digital Signal Processor

  • 1873.07KB

  • Motorola

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Signals/Connections
Table 1-9.
Name
General-
Purpose I/O
PC13
Port C Signals (Continued)
Peripheral Controller:
Dedicated I/O
Protocol
SI1: L1ST4
Dedicated
I/O Data
Direction
Output
Description
Serial Interface 1: Layer 1 Strobe 4
The MSC8101 time-slot assigner supports up to four strobe outputs that
can be asserted on a bit or byte basis. The strobe outputs are useful for
interfacing to other devices that do not support the multiplexed interface or
for enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also generate output wave forms for such
applications as stepper-motor control.
SCC2: Clear to Send, Collision
Typically used in conjunction with RTS. The MSC8101 SCC2 transmitter
sends out a request to send data signal (RTS). The request is accepted
when CTS is returned low. CLSN is the signal used in Ethernet mode. See
also PC28.
FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 1
This is master transmit address bit 1.
FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 1
This is slave transmit address bit 1.
Serial Interface 1: Layer 1 Strobe 3
The MSC8101 time-slot assigner supports up to four strobe outputs that
can be asserted on a bit or byte basis. The strobe outputs are useful for
interfacing to other devices that do not support the multiplexed interface or
for enabling/disabling three-state I/O buffers in a multiple-transmitter
architecture. These strobes can also generate output wave forms for such
applications as stepper-motor control.
SCC2: Carrier Detect, Request Enable
Typically used in conjunction with RTS supported by SCC2. The MSC8101
SCC2 transmitter requests to the receiver that it sends data by asserting
RTS low. The request is accepted when CTS is returned low.
FCC1: UTOPIA Multi-PHY Master Receive Address Bit 1
This is master receive address bit 1.
FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 1
This is slave receive address bit 1.
SCC2: CTS,CLSN
Input
FCC1:TXADDR1
UTOPIA master
FCC1: TXADDR1
UTOPIA slave
PC12
SI1: L1ST3
Output
Input
Output
SCC2: CD, RENA
Input
FCC1: RXADDR1
UTOPIA master
FCC1: RXADDR1
UTOPIA slave
Output
Input
MSC8101 Technical Data, Rev. 16
1-30
Freescale Semiconductor

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