Physical and Electrical Specifications
Figure 2-12
shows Host DMA read timing.
HREQ
(Output)
64
44a
HACK
RX[0鈥?]
Read
63
44b
50
49
HD[0鈥?5]
(Output)
Data
Valid
51
52
Figure 2-12.
Host DMA Read Timing Diagram, HPCR[OAD] = 0
Figure 2-13
shows Host DMA write timing.
HREQ
(Output)
64
45
HACK
TX[0鈥?]
Write
63
46
47
48
HD[0鈥?5]
(Output)
Data
Valid
Figure 2-13.
Host DMA Write Timing Diagram, HPCR[OAD] = 0
MSC8101 Technical Data, Rev. 16
2-20
Freescale Semiconductor