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MSC8101 Datasheet

  • MSC8101

  • Networking Digital Signal Processor

  • 1873.07KB

  • Motorola   Motorola

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AC Timings
2.6.6
No.
39
CPM Timings
Table 2-20.
CPM Input Characteristics
Typical
10
5
0
3
20
5
0
5
5
5
10
3
Characteristic
FCC input set-up time before low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
FCC input hold time after low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
SCC/SMC/SPI/I
2
C input set-up time before low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
SCC/SMC/SPI/I
2
C input hold time after low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
TDM input set-up time before low-to-high serial clock transition
TDM input hold time after low-to-high serial transition
PIO/TIMER/DMA input set-up time before low-to-high serial clock transition
PIO/TIMER/DMA input hold time after low-to-high serial clock transition
FCC, SCC, SMC, SPI, I
2
C are Non-Multiplexed Serial Interface signals.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
18
19
20
21
22
23
Note:
Table 2-21.
No.
41
CPM Output Characteristics
Min
0
2
0
0
5
1
Characteristic
FCC output delay after low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial input clock)
SCC/SMC/SPI/I
2
C output delay after low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial input clock)
TDM output delay after low-to-high serial clock transition
PIO/TIMER/DMA output delay after low-to-high serial clock transition
FCC, SCC, SMC, SPI, I
2
C are non-multiplexed serial interface signals.
Max
6
18
20
30
15
14
Unit
ns
ns
ns
ns
ns
ns
38
40
42
Note:
BRGxO
17a
29a
FCC inputs
41a
FCC outputs
Figure 2-14.
FCC Internal Clock Diagram
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
2-21

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