鈥?/div>
SC140 core
鈥?Architecture optimized for efficient C/C++ code compilation
鈥?Four 16-bit ALUs and two 32-bit AGUs
鈥?1200 DSP MMACS running at 300 MHz
鈥?Very low power dissipation
鈥?Variable-length execution set (VLES) execution model
鈥?JTAG/Enhanced OnCE debug port
Communications processor module (CPM)
鈥?Programmable protocol machine using a 32-bit RISC engine
鈥?155 Mbps ATM interface (including AAL 0/1/2/5)
鈥?10/100 Mbit Ethernet interface
鈥?Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface
鈥?HDLC support up to T3 rates, or 256 channels
64- or 32-bit wide bus interface
鈥?Support for bursts for high efficiency
鈥?Glueless interface to 60x-compatible bus systems
鈥?Multi-master support
Enhanced filter coprocessor (EFCOP)
鈥?Independently and concurrently executes long filters (such as echo cancellation)
鈥?Runs at 250/275/300 MHz and provides 250/275/300 MMACS performance
Programmable memory controller
鈥?Control for up to eight banks of external memory
鈥?User-programmable machines (UPM) allowing glueless interface to various memory types (SRAM, DRAM,
EPROM, and Flash memory) and other user-definable peripherals
鈥?Dedicated pipelined SDRAM memory interface
Large internal SRAM
鈥?256K 16-bit words (512 KB)
鈥?Unified program and data space configurable by the application
鈥?Word and byte addressable
DMA controller
鈥?16 DMA channels, FIFO based, with burst capabilities
鈥?Sophisticated addressing capabilities
Small foot print package
鈥?17 mm
脳
17 mm lidded FC-PBGA package
Very low power consumption
鈥?Separate power supply for internal logic (1.6 V) and for I/O (3.3 V)
Enhanced 16-bit parallel host interface (HDI16)
鈥?Supports a variety of microcontroller, microprocessor, and DSP bus interfaces
Phase-lock loops (PLLs)
鈥?System PLL
鈥?CPM DPLLs (SCC and SCM)
Process technology
鈥?0.13 micron copper interconnect process technology
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MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
iii
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