AC Timings
DLLIN
10
AACK/ARTRY/TA/TEA/DBG/BG/BR
PSDVAL/ABB/DBB/TS inputs
11
10
12
Data bus inputs鈥攏ormal mode
10
Data bus inputs鈥擡CC and parity modes
DP inputs
Address bus/TT[0鈥?]/TC[0鈥?]/TBST/TSIZ[0鈥?]/GBL inputs
PUPMWAIT/IRQn input
13
14
15
16
10
31
PSDVAL/TEA/TA outputs
32
Address bus/TT[0鈥?]/TC[0鈥?]/TBST/TSIZ[0鈥?]/GBL/BADDR[27鈥?1] outputs
Data bus outputs
DP outputs
33a
33b
Memory controller/ALE signals
34
35
AACK/ARTRY/ABB/TS/DBG/BG/BR/DBB/CS signals
36
All other normal mode outputs
Figure 2-6.
Bus Signal Timing
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
2-15