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MSC8101 Datasheet

  • MSC8101

  • Networking Digital Signal Processor

  • 1873.07KB

  • Motorola   Motorola

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AC Timings
2.6 AC Timings
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and
inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50
鈩?/div>
transmission line.
2.6.1
Output Buffer Impedances
Table 2-9.
Output Buffers
Output Buffer Impedances
Typical Impedance (鈩?
35
35
55
System Bus
Memory Controller
Parallel I/O
Note:
These are typical values at 65掳C. The impedance may vary by 卤25% depending on device process and operating temperature.
2.6.2
Clocking and Timing Characteristics
Table 2-10.
Characteristic
System Clock Parameters
Minimum
鈥?/div>
18
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Maximum
0.5
75
5
2
(0.01/CLKOUT) + CLKIN jitter
5
Unit
ns
MHz
ns
ns
ns
ns
Phase Jitter between BCLK and DLLIN
CLKIN frequency
1,2
CLKIN slope
DLLIN slope
CLKOUT frequency jitter
Delay between CLKOUT and DLLIN
Notes:
1.
2.
Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the frequency after the
predivider (SPLLMFCLK) higher than 18 MHz.
CLKIN should have a 50%
卤
5% duty cycle.
Table 2-11.
Clock Ranges
Maximum Rated Core Frequency
Clock
Symbol
All
Min
Max. Values for SC140 Clock Rating of:
250 MHz
83.3
31.25
83.3 MHz
83.3 MHz
166.7 MHz
250 MHz
275 MHz
91.67 MHz
34.38 MHz
91.67 MHz
91.67 MHz
183.3 MHz
275 MHz
300 MHz
100 MHz
37.5 MHz
100 MHz
100 MHz
200 MHz
300 MHz
Input Clock
SPLL MF Clock
Bus/Output
Serial Communications Controller
Communications Processor Module
SC140 Core
CLKIN
SPLLMFCLK
BCLK
CLKOUT
SCLK
CPMCLK
DSPCLK
18 MHz
18 MHz
18 MHz
35 MHz
70 MHz
72 MHz
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
2-7

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