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MSC8101 Datasheet

  • MSC8101

  • Networking Digital Signal Processor

  • 1873.07KB

  • Motorola

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Physical and Electrical Specifications
Table 2-11.
Clock Ranges (Continued)
Maximum Rated Core Frequency
Clock
Symbol
All
Min
Max. Values for SC140 Clock Rating of:
250 MHz
83.3 MHz
20.83 MHz
5.21 MHz
1.3 MHz
275 MHz
91.67 MHz
22.91 MHz
5.73 MHz
1.43 MHz
300 MHz
100 MHz
25 MHz
6.25 MHz
1.56 MHz
Baud Rate Generator
鈥?For BRG DF = 4
鈥?For BRG DF = 16 (default)
鈥?For BRG DF = 64
鈥?For BRG DF = 256
BRGCLK
36 MHz
9 MHz
2.25 MHz
562.5 KHz
2.6.3
Reset Timing
The MSC8101 has several inputs to the reset logic:
鈥?Power-on reset (
PORESET
)
鈥?External hard reset (
HRESET
)
鈥?External soft reset (
SRESET
)
Asserting an external
PORESET
causes concurrent assertion of an internal
PORESET
signal,
HRESET
, and
SRESET
.
When the external
PORESET
signal is deasserted, the MSC8101 samples several configuration pins:
鈥?/div>
RSTCONF
鈥攄etermines whether the MSC8101 is a master (0) or slave (1) device
鈥?/div>
DBREQ
鈥攄etermines whether to operate in normal mode (0) or invoke the SC140 debug mode (1)
鈥?/div>
HPE
鈥攄isable (0) or enable (1) the host port (HDI16)
鈥?/div>
BTM[0鈥?]
鈥攂oot from external memory (00) or the HDI16 (01)
All these reset sources are fed into the reset controller, which takes different actions depending on the source of the
reset. The reset status register indicates the last sources to cause a reset.
Table 2-12
describes reset causes.
Table 2-12.
Name
Power-on reset
(PORESET)
Hard reset
(HRESET)
Soft reset
(SRESET)
Reset Causes
Description
Direction
Input
Input/Output
PORESET initiates the power-on reset flow that resets all the MSC8101s and configures
various attributes of the MSC8101, including its clock mode.
The MSC8101 can detect an external assertion of HRESET only if it occurs while the
MSC8101 is not asserting reset. During HRESET, SRESET is asserted. HRESET is an open-
drain pin.
The MSC8101 can detect an external assertion of SRESET only if it occurs while the
MSC8101 is not asserting reset. SRESET is an open-drain pin.
Input/Output
2.6.3.1 Reset Operation
The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the appropriate logic
modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized
only on hard reset. Soft reset initializes the internal logic while maintaining the system configuration. The
MSC8101 has three mechanisms for reset configuration: host reset configuration, hardware reset configuration, and
reduced reset configuration.
MSC8101 Technical Data, Rev. 16
2-8
Freescale Semiconductor

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